Monolithic switching devices, using both time and space switching, are the crucial components to build large digital Cross Connects. A given switch can have a number of physical channels NCH, each carrying a number of time-slots NTS. If each time slot in each output channel can carry data drawn from any time-slot of any of the input channels, the switch is fully non-blocking. The typical implementations of the time-space switch are two: Mux-based and RAM-based. As far as Mux-based switches are concerned, the limitation, in case of high throughput switches, is mainly due to the huge number of connections which cause drastic routing congestion in design layout. The advantage of a RAM-based architecture is the reduction of the number of connections in the switch design by the means of redundant memory elements; however, the limitation in this latter case is the huge quantity of RAM.
In a RAM-based switch the interchangeable data, consisting of (NCH*NTS) time-slots, are sequentially written in a data matrix D (DM1) with NC columns and NR rows: obviously NC*NR≧NCH*NTS. Physically, each column is a RAM element (Ram1 ˜Ram5) and can provide only a single time slot every clock cycle because of time-space switch synchronous nature (FIG. 1): the access method is called SW-RR (Sequential Write, Random Read).
From here onwards, we assume that the RAM blocks are dual port R+W and that the same clock frequency is used to read and write the time-slots. A high number of read ports and a read frequency multiple of the write frequency can provide benefit to both this invention and standard architectures to the same extent. However, a description based on the above mentioned assumption may be easier to understand.
If NR>1, then a single data matrix is clearly blocking for any read of more than one time-slot from the same column of the matrix; the switch becomes non-blocking at the level of a single time-slot when the data matrix is replicated. The case NR=1 is outside the scope of this description, because the architecture becomes fully spatial.
In common RAM-based architectures the data for switch connectivity is stored in a data matrix with NCH columns and NTS rows and non-blocking capability is achieved by replicating the data matrix NCH times. For example, as illustrated in FIG. 2, in the case of NCH=5 and NTS=5, five data matrices (DM21-DM 25) are prepared. Each column of the data matrices (DM21-DM 25) is a RAM element and can provide only a single time slot every clock cycle because of time-space switch synchronous nature. It is worth noting that, if NTS<NCH, then NTS replicas are sufficient for non-blocking, but NTS makes the output multiplexing circuitry more complex or even practically unfeasible for NTS as high as 48, which is a common value. Therefore the standard implementation uses NCH replicas of the data matrix. This means that the physical memory size grows with NCH2 which drastically limits the throughput achievable in monolithic form because of the die size and power requirements. Therefore, it is very difficult to reach a switch throughput higher than 200 Gbp/s.
For example, in a practical case of a 144×144 2.5 Gb/s (STS-48) grooming switch with STS-1 granularity, NCH=144 and NTS=48 this standard implementation would require 8 Mbit split into 144 dual port RAMs (or equivalent size of RAMs with higher number of ports).